Design for Manufacturability and Yield for Nano-Scale CMOS by Charles Chiang, Jamil Kawa

By Charles Chiang, Jamil Kawa

This ebook walks the reader via the entire points of manufacturability and yield in a nano-CMOS strategy. It covers all CAD/CAE facets of a SOC layout stream and addresses a brand new subject (DFM/DFY) severe at ninety nm and past. This publication is a needs to learn booklet the intense practising IC clothier and a very good primer for any graduate scholar purpose on having a occupation in IC layout or in EDA device improvement.

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Additional resources for Design for Manufacturability and Yield for Nano-Scale CMOS (Integrated Circuits and Systems)

Example text

That is, reducing the critical area of any particular layer of an individual standard cell or of a whole routed design. In Chapter 6 we will present a comprehensive design flow view of yield yet it is important to emphasize at this point that yield optimization steps are all interlinked and must be dealt with collectively through a weighted total yield model. An example of that would be poly to poly spacing in a standard cell where the short CA for poly is improved but the diffusion capacitance of the impacted node is higher and thus might impact the performance of the cell, etc.

An interesting issue arises when some alternatives have conflicting outcomes. An example of that will be the routing area where a procedure such as wire widening might improve the CA “opens” score of the design but worsens the CA “shorts” score of the design. This is why this methodology focuses at optimizing a weighted function of yield rather than maximizing yield. Maximizing yield might be too costly and might not be desirable. An obvious example of that would be using a 100% DFM and DFY: Fully Intertwined 19 defect free mask!

7 illustrates that there is a lot that can be done to improve the CA for opens and shorts for poly and metal 1 for a standard cell. Unfortunately most automatic layout generation tools are not that sophisticated and thus hand packing of the layout might be needed but it is worthwhile spending the time to do so as the library is built once and is used many times over. Not all cells are as easy to exploit as the example we just gave. Some cells are pretty dense and hard to route in the first place.

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